As integrated circuits advance to very-large-scale integration (VLSI), their internal densities increase, and the numbers of included devices grow, making the surfaces of wafers unable to provide enough areas for fabrication of required interconnection lines.
In order to meet the requirement of interconnection lines with shrunk devices, designing multi-layer metal interconnection lines with two or more layers has become a common approach in the field of VLSI. Currently, interconnections between different metal layers, or between metal layers and substrates are achieved by a contact hole structure. The contact hole structure is formed by: forming an opening in a dielectric layer between metal layers or between a metal layer and a substrate; and filling the contact hole with an electrically conductive material. More information on existing solutions for forming contact holes can be found in Chinese Patent Application No. 200610030809.4.
Referring FIG. 1, an existing process for forming a contact hole structure includes the following steps:                step S101, providing a substrate;        step S102: forming a metal layer on the substrate;        step S103, forming a dielectric layer covering the metal layer on the substrate;        step S104, etching the dielectric layer to form a contact hole exposing the metal layer below;        step S105, performing plasma processing on the surface of the metal layer;        step S106, forming a barrier layer on the sidewalls of the contact hole and the surface of the substrate; and        step S107, filling the contact hole with an electrically conductive material.        
The process for forming a contact hole structure described above may damage the sidewalls in the dielectric layer, degrading contact performance of the contact hole, thereby increasing the resistance of an electrically conductive plug subsequently formed in the contact hole, and affecting performance of the device.